Xilinx Virtex-5 RocketIO GTP User Manual page 304

Appendix D: DRP Address Map of the GTP_DUAL Tile
Table D-9: DRP Addresses 30 through 37 (Continued)
Bit
30
CHAN_ DEC_VALID_
7 BOND_SEQ_2 COMMA_
_2_0[3] ONLY_0
CHAN_
8 BOND_SEQ_2 PCOMMA_
_2_0[2] DETECT_0
CHAN_
9 BOND_SEQ_2 MCOMMA_
_2_0[1] DETECT_0
CHAN_
COMMA_
10 BOND_SEQ_2
DOUBLE_0
_2_0[0]
CHAN_ COMMA_
11 BOND_SEQ_2 10B_ENABLE
_3_0[9]
COMMA_
MCOMMA_
12 10B_ENABLE
DETECT_0
MCOMMA_ COMMA_
13 10B_VALUE_ 10B_ENABLE
0[0]
MCOMMA_ COMMA_
14 10B_VALUE_ 10B_ENABLE
0[1]
MCOMMA_ COMMA_
15 10B_VALUE_ 10B_ENABLE
0[2]
Table D-10: DRP Addresses 38 through 3F
Bit
38
CLK_COR_
CLK_COR_
0 MAX_LAT_
SEQ_1_1_0[8]
CLK_COR_
CLK_COR_
1 MAX_LAT_
SEQ_1_1_0[9]
CLK_COR_ CLK_COR_
2 REPEAT_WAIT MAX_LAT_
_0[0]
CLK_COR_ CLK_COR_
3 REPEAT_WAIT MAX_LAT_
_0[1]
304
31 32
COM_BURST CLK_COR_
_VAL_0[2] SEQ_2_4_0[9]
DEC_
COM_BURST CLK_COR_
_VAL_0[3] SEQ_2_3_0[0]
DEC_
CLK_COR_ CLK_COR_
SEQ_2_USE_0 SEQ_2_3_0[1]
CLK_COR_
CLK_COR_
SEQ_2_
SEQ_2_3_0[2]
ENABLE_0[1]
CLK_COR_
CLK_COR_
SEQ_2_
SEQ_2_3_0[3]
_0[0] ENABLE_0[2]
CLK_COR_
CLK_COR_
SEQ_2_
SEQ_2_3_0[4]
_0[1] ENABLE_0[3]
CLK_COR_
CLK_COR_
SEQ_2_
SEQ_2_3_0[5]
_0[2] ENABLE_0[4]
CLK_COR_ CLK_COR_
SEQ_2_4_0[0] SEQ_2_3_0[6]
_0[3]
CLK_COR_ CLK_COR_
SEQ_2_4_0[1] SEQ_2_3_0[7]
_0[4]
39 3A
CHAN_
BOND_SEQ_2
_ENABLE_
0[1]
0[3]
CHAN_
BOND_SEQ_2
_ENABLE_
0[2]
0[4]
Do Not
Modify
0[3]
OOBDETECT_
THRESHOLD
0[4] _0[0]
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Address
33 34
CLK_COR_
CLK_COR_
SEQ_2_2_0[5] ENABLE_
CLK_COR_
CLK_COR_
SEQ_2_2_0[6]
ENABLE_0[3]
CLK_COR_
CLK_COR_
SEQ_2_2_0[7]
ENABLE_0[4]
CLK_COR_ CLK_COR_
SEQ_2_2_0[8] SEQ_1_4_0[0]
CLK_COR_ CLK_COR_
SEQ_2_2_0[9] SEQ_1_4_0[1]
CLK_COR_ CLK_COR_
SEQ_2_1_0[0] SEQ_1_4_0[2]
CLK_COR_ CLK_COR_
SEQ_2_1_0[1] SEQ_1_4_0[3]
CLK_COR_ CLK_COR_
SEQ_2_1_0[2] SEQ_1_4_0[4]
CLK_COR_ CLK_COR_
SEQ_2_1_0[3] SEQ_1_4_0[5]
Address
3B 3C
TRANS_
Do Not
TIME_TO_P2 TIME_NON_
Modify
_0[3]
TRANS_
Do Not
TIME_TO_P2 TIME_NON_
Modify
_0[4]
TRANS_
Do Not
TIME_TO_P2 TIME_NON_
Modify
_0[5]
TRANS_
Do Not
TIME_TO_P2 TIME_NON_
Modify
_0[6]
Virtex-5 RocketIO GTP Transceiver User Guide
35 36
SEQ_1_ CLK_COR_ CLK_COR_
SEQ_1_3_0[3] SEQ_1_2_0[9]
0[2]
CLK_COR_ CLK_COR_
SEQ_1_
SEQ_1_3_0[4] SEQ_1_1_0[0]
CLK_COR_ CLK_COR_
SEQ_1_
SEQ_1_3_0[5] SEQ_1_1_0[1]
CLK_COR_ CLK_COR_
SEQ_1_3_0[6] SEQ_1_1_0[2]
CLK_COR_ CLK_COR_
SEQ_1_3_0[7] SEQ_1_1_0[3]
CLK_COR_ CLK_COR_
SEQ_1_3_0[8] SEQ_1_1_0[4]
CLK_COR_ CLK_COR_
SEQ_1_3_0[9] SEQ_1_1_0[5]
CLK_COR_ CLK_COR_
SEQ_1_2_0[0] SEQ_1_1_0[6]
CLK_COR_ CLK_COR_
SEQ_1_2_0[1] SEQ_1_1_0[7]
3D 3E
TRANS_ TRANS_
SATA_MIN_
TIME_FROM
WAKE_0[2]
P2_0[3] _P2_0[3]
TRANS_ TRANS_
SATA_MIN_
TIME_FROM
WAKE_0[3]
P2_0[4] _P2_0[4]
TRANS_ TRANS_
SATA_MIN_
TIME_FROM
WAKE_0[4]
P2_0[5] _P2_0[5]
TRANS_ TRANS_
SATA_MIN_
TIME_FROM
WAKE_0[5]
P2_0[6] _P2_0[6]
UG196 (v1.3) May 25, 2007
R
37
3F