Xilinx Virtex-5 RocketIO GTP User Manual page 83

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Table 5-11: Basic Power Control Functions Summary
Function
REFCLK Power Control
PLL Power Control
TX Power Control
(1)
RX Power Control
Notes:
1. When RXPOWERDOWN[1:0] is set to 11, which is the lowest power state (P2), then RXRECCLK of this transceiver is
indeterminate. RXXRECCLK of this GTP transceiver is either a static 1 or a static 0.
REFCLK Power Control
To activate the REFCLK power control mode, the active-Low REFCLKPOWERDNB signal
is asserted. When REFCLKPOWERDNB is asserted, toggling of all circuitry clocked by the
REFCLK input is suppressed, including the shared PMA PLL and all clocks derived from
it. In addition, asserting REFCLKPOWERDNB disables the dedicated clock routing
circuitry associated with that tile. If the GTP_DUAL tiles share a common reference,
REFCLK is suppressed to tiles that are downstream in the clock routing chain.
illustrates how the dedicated clock routing blocks forward REFCLKs between GTP_DUAL
tiles.
Recovery from this power state is indicated by the assertion of the PLLLKDET signal on the
tile whose
clocks are affected.
PLL Power Control
To activate the PLL power control mode, the active-High PLLPOWERDOWN signal is
asserted. When PLLPOWERDOWN is asserted, the shared PMA PLL and all clocks
derived from it are stopped.
Recovery from this power state is indicated by the assertion of the PLLLKDET signal on the
tile whose
TX and RX Power Control
When the TX and RX power control signals are used in non-PCI Express implementations,
the TXPOWERDOWN and RXPOWERDOWN can be used independently. However,
when these interfaces are used in non-PCI Express applications, only two power states are
supported, as shown in
following must be True:
•
•
•
•
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Controlled By
REFCLKPOWERDNB
PLLPOWERDOWN
TXPOWERDOWN[1:0]
RXPOWERDOWN[1:0]
REFCLKPOWERDNB signal is asserted and all downstream tiles whose reference
REFCLKPOWERDNB signal is asserted .
Table
TXPOWERDOWN[1] and TXPOWERDOWN[0] are connected together.
RXPOWERDOWN[1] and RXPOWERDOWN[0] are connected together.
TXDETECTRX must be strapped Low.
TXELECIDLE must be strapped to TXPOWERDOWN[1] and TXPOWERDOWN[0].
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Relative
Power
Savings
TX and RX for both transceivers in a
tile, and all downstream GTP_DUAL
tiles sharing that REFCLK
TX and RX for both transceivers in a
GTP_DUAL tile
TX in a single transceiver
RX in a single transceiver.
5-12. When using this power control mechanism, the
Power Control
Recovery
Affects
Figure 5-3
Time
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