Examples; Configuring The Shared Pll For Xaui - Xilinx Virtex-5 RocketIO GTP User Manual

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Chapter 5: Tile Features
Table 5-3: Communication Standards (Continued)
TX/RX
Line
USRCLK
Standard
Rate
Frequency
[Gb/s]
2.4576
245.76
(2)
CPRI
1.2288
122.88
0.6144
1.536
(2)
OBSAI
0.768
(3)
SFI-5
3.125
(3)
TFI-5
3.1104
INTDATAWIDTH = 0 (8-bit internal datapath) → (DIV = 4)
OC12
0.62208
OC48
2.488
(3)
SFI-5
2.488
(3)
SPI-5
2.488
(3)
TFI-5
2.488
Notes:
1. See
"Parallel In to Serial Out (PISO)," page 110
2. Synchronous system.
3. Maximum data rate.
4. Other frequency is 0.1% lower.
See

Examples

Configuring the Shared PLL for XAUI

The three methods to configure the shared PLL for XAUI are described below:
1.
2.
3.
64
Reference
Clock
PLL Clock
Frequency
Frequency
REFCLK
[GHz]
[MHz]
[MHz]
122.88
1.2288
122.88
1.2288
61.44
122.88
1.2288
153.6
153.6
1.536
76.8
153.6
1.536
312.5
156.25
1.5625
311.04
155.52
1.5552
77.76
155.52
1.24416
311.04
155.52
1.24416
311.04
155.52
1.24416
311.04
155.52
1.24416
311.04
155.52
1.24416
and
"Serial In to Parallel Out (SIPO)," page 141
"Clocking," page 68
for details on supplying CLKIN to the shared PMA PLL.
Use the RocketIO GTP Wizard.
The wizard includes a protocol file for XAUI that allows it to automatically configure
the GTP_DUAL primitive for use in a XAUI design.
Use the settings from
Table
Table 5-3
includes the settings for common configurations of popular protocols. XAUI
settings are included in
encoding.
Use
Equation 5-1
as described in the following steps:
a.
Determine the required line rates.
For XAUI, both TX and RX use a line rate of 3.125 Gb/s.
b. Determine the internal datapath width.
Because XAUI is an 8B/10B-encoded standard, an internal datapath width of
10 bits is required. See
www.xilinx.com
Reference Clock
Feedback Loop
Divider Setting
Divider Setting
PLL_DIVSEL_REF
PLL_DIVSEL_FB
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
5-3.
Table
5-3, along with other protocols that use 8B/10B
"Configurable 8B/10B Encoder," page 98
Virtex-5 RocketIO GTP Transceiver User Guide
Divider Settings
PLL_RXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_COMM_OUT
1
2
4
2
4
1
1
4
1
1
1
1
for more details about the divider setting.
and
UG196 (v1.3) May 25, 2007
R
(1)

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