Xilinx Virtex-7 FPGA VC7203 Getting Started Manual
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Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

Characterization kit ibert
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Virtex-7 FPGA VC7203
Characterization Kit IBERT
Getting Started Guide
UG847 (Vivado Design Suite v2015.1) April 27, 2015

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Summary of Contents for Xilinx Virtex-7 FPGA VC7203

  • Page 1 Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Guide UG847 (Vivado Design Suite v2015.1) April 27, 2015...

  • Page 2: Revision History

    Started Guide. The ZIP project file name changed to rdf0272-vc7203-ibert-2013-3.zip. In Figure 1-11, Digilent JTAG cable changed to Xilinx TCF agent. Figure 1-30 was renamed Design Sources File Hierarchy. Figure 1-31, Synthesize Out-Of-Context Module was deleted. Updated Appendix A, Additional Resources and Legal Notices links.

  • Page 3: Table Of Contents

    Xilinx Resources ........

  • Page 4: Overview

    Setting Up the Vivado Design Suite, page 14 Starting the SuperClock-2 Module, page 17 Viewing GTX Transceiver Operation, page 22 Closing the IBERT Demonstration, page 24 VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...

  • Page 5: Requirements

    • Vivado Design Suite software 2015.1 The hardware and software required to rebuild the IBERT demonstration designs are: • PC with a version of the Windows operating system supported by Xilinx Vivado Design Suite • Vivado Design Suite software 2015.1 Setting Up the VC7203 Board This section describes how to set up the VC7203 board.

  • Page 6: Extracting The Project Files

    The Vivado project files required to run the IBERT demonstrations are located in rdf0272-vc7203-ibert-2015-1.zip on the SD card provided with the VC7203 board. They are also available online at the Virtex-7 FPGA VC7203 Characterization Kit documentation website. The ZIP file contains these files: •...
  • Page 7 1. Connect the Secure Digital memory card to the host computer. 2. Locate the file rdf0272-vc7203-ibert-2015-1.zip on the Secure Digital memory card. 3. Unzip the files to a working directory on the host computer. VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...

  • Page 8: Running The Gtx Ibert Demonstration

    All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector pad which interfaces with Samtec BullsEye connectors. Figure 1-2 A shows the connector pad. Figure 1-2 B shows the connector pinout. VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 9 For the GTX IBERT demonstration, the output clock frequencies are preset to 156.25 MHz. For more information regarding the SuperClock-2 module, see HW-CLK-101-SCLK2 SuperClock-2 Module User Guide (UG770) [Ref VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 10 X-Ref Target - Figure 1-5 Figure 1-5: BullsEye Connector Attached to Quad 115 VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 11 To ensure good connectivity, it is recommended that the adapters be secured with a wrench; Note: however, do not over-tighten the SMAs. X-Ref Target - Figure 1-6 Figure 1-6: SMA F-F Adapter VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 12 VC7203 board with the cable connections required for the Quad 115 GTX IBERT demonstration. X-Ref Target - Figure 1-8 Figure 1-8: Cable Connections for Quad 115 GTX IBERT Demonstration VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 13 The FPGA can also be configured through the Vivado Design Suite software using the .bit files and .ltx probe files available on the SD card, or online (as collection rdf0272-vc7203-ibert-2015-1.zip) at the Virtex-7 FPGA VC7203 Characterization Kit documentation website.
  • Page 14 1. Start Vivado Design Suite on the host computer and click Flow > Open Hardware Manager (highlighted in Figure 1-10). X-Ref Target - Figure 1-10 Figure 1-10: Vivado Design Suite, Open Hardware Manager VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 15 3. An Open Hardware Target wizard pops up. Click Next on the first window. 4. In the Hardware Server Settings window, select Local server (target is on local machine). Click Next to open the server and connect to the Xilinx TCF JTAG cable. VC7203 IBERT Getting Started Guide www.xilinx.com...
  • Page 16 Figure 1-12: Select Hardware Target 6. In the Open Hardware Target Summary window, click Finish. The wizard closes and the Vivado tool opens the hardware target. VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 17 Device Properties window, enter the file path to the Q115 Probes file (vc7203_ibert_q115_debug_nets.ltx) in the extracted IBERT files from the SD card (Figure 1-13). X-Ref Target - Figure 1-13 Figure 1-13: Adding the Probes File VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 18 If the FPGA was not programmed using the SD card, provide both the programming and Note: the probes files, and then select Program Device. X-Ref Target - Figure 1-14 Figure 1-14: Program/Refresh Device VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 19 Script window, navigate to the setup_scm2_156_25.tcl script in the extracted files and click OK. X-Ref Target - Figure 1-15 Figure 1-15: Run Tcl Script VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 20 SuperClock-2 frequencies and their associated ROM addresses is provided in Table 1-2. X-Ref Target - Figure 1-16 Figure 1-16: SuperClock-2 Module VIO Core VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 21 Create Links, or by clicking the Create Links button (Figure 1-17). X-Ref Target - Figure 1-17 Figure 1-17: Serial I/O Analyzer - Create Links VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 22 MGT_X1Y8/TX to MGT_X1Y8/RX ° MGT_X1Y9/TX to MGT_X1Y9/RX ° MGT_X1Y10/TX to MGT_X1Y10/RX ° MGT_X1Y11/TX to MGT_X1Y11/RX ° X-Ref Target - Figure 1-18 Figure 1-18: Create Links Window VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 23 Make sure the blue elastomer seal is connected to the bottom of the BullsEye cable and the cable is firmly connected and flush on the board. VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...

  • Page 24: Superclock-2 Frequency Table

    167.330 Generic 205.000 Display Port 81.000 OTU-2 669.310 Generic 210.000 Display Port 135.000 OTU-3 168.050 Generic 215.000 Display Port 162.000 OTU-4 174.690 Generic 220.000 VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 25 Generic 470.000 Generic 345.000 Generic 410.000 Generic 475.000 Generic 350.000 Generic 415.000 Generic 480.000 Generic 355.000 Generic 420.000 Generic 485.000 Generic 360.000 Generic 425.000 VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...

  • Page 26: Creating The Gtx Ibert Core

    2. In the Vivado design tools window, click the Manage IP icon (highlighted in Figure 1-20), then select New IP Location. X-Ref Target - Figure 1-20 Figure 1-20: Vivado Design Suite Initial Window VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 27 Part field. A Select Device window pops up. Use the drop-down menu items to narrow the choices. Select the xc7vx485tffg1761-3 device (Figure 1-21). Click OK. X-Ref Target - Figure 1-21 Figure 1-21: Select Device VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 28 (Figure 1-22). Click Finish. Make sure the directory name does not include spaces. Note: X-Ref Target - Figure 1-22 Figure 1-22: Manage IP Settings VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 29 6. In the Vivado IP Catalog window, open the Debug & Verification folder, then open the Debug folder, and double-click IBERT 7 Series GTX (Figure 1-23). X-Ref Target - Figure 1-23 Figure 1-23: IP Catalog VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 30 12.5, then use the drop-down to change the Refclk (MHz) to 156.250. Keep defaults for other fields (Figure 1-24). X-Ref Target - Figure 1-24 Figure 1-24: Customize IP - Protocol Definition VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 31 Protocol Selected next to QUAD_113, and select MGTREFCLK1 113 in the Refclk Selection drop-down menu (Figure 1-25). X-Ref Target - Figure 1-25 Figure 1-25: Customize IP - Protocol Selection VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 32 1-26). Press OK. A Generate Output Products window opens. Leave the defaults unchanged, and press Generate. X-Ref Target - Figure 1-26 Figure 1-26: Customize IP - Clock Settings VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 33 1-27). Specify a location to save the design, press OK, and the Example Design design opens in a new Vivado design tools window. X-Ref Target - Figure 1-27 Figure 1-27: Open IP Example Design VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 34 OK. The SuperClock-2 Module Design Sources and Constraints are automatically added to the example design (Figure 1-28). X-Ref Target - Figure 1-28 Figure 1-28: Sources after Running add_scm2.tcl VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 35 IBERT wrapper (Figure 1-29). Click File > Save File. X-Ref Target - Figure 1-29 Figure 1-29: SuperClock-2 in the Example IBERT Wrapper VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 36 13. In the Sources window, Design Sources should now reflect that the SuperClock-2 module is part of the example IBERT design (Figure 1-30). X-Ref Target - Figure 1-30 Figure 1-30: Design Sources File Hierarchy VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 37 15. When synthesis is done, a Synthesis Complete window opens. Select Open Synthesized Design and click OK (Figure 1-32). X-Ref Target - Figure 1-32 Figure 1-32: Synthesis Completed VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 38 1-34). A window pops up asking if it is okay to launch implementation. Click Yes. X-Ref Target - Figure 1-34 Figure 1-34: Generate Bitstream VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...
  • Page 39 19. When the bitstream generation completes, navigate to the project directory and locate the generated bitstream file. When implementation completes, navigate to: \ibert_7series_gtx_0\ibert_7series_gtx_0_example\ibert_7series_g tx_0_example.runs\impl_1 directory to locate the generated bitstream. VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...

  • Page 40: Appendix A: Additional Resources And Legal Notices

    Virtex-7 FPGA VC7203 Characterization Kit documentation Virtex-7 FPGA VC7203 Characterization Master Answer Record (AR 52383) These Xilinx documents and sites provide supplemental material useful with this guide: 1. VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board User Guide (UG957) 2. HW-CLK-101-SCLK2 SuperClock-2 Module User Guide (UG770) 3.

  • Page 41: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 42 Customer. For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products.
  • Page 43 Appendix B: Warranty VC7203 IBERT Getting Started Guide www.xilinx.com Send Feedback UG847 (Vivado Design Suite v2015.1) April 27, 2015...

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