Xilinx Virtex-5 RocketIO GTP User Manual page 227

R
Several protocols including PCI Express and SATA specify ranges for blocking capacitors
in applications. This is done not only to simplify compliance but also to ensure that the link
presence detection features included in these specifications work correctly.
Table 11-1: PCI Express and SATA Blocking Capacitor Values
The blocking capacitor when combined with the termination resistance acts as a high-pass
filter.
capacitors are not shown in this model because they do not play a significant role in
blocking DC currents from the external link as described in
Equalization," page 125
Problems occur when the line is held in the on state for an extended period of time. When
this happens, charge accumulates on the blocking capacitors and a DC offset is added or
subtracted from V2. This offset results in what is known as baseline wander (see
Figure
The effect of baseline wander is to shift the signal with respect to the threshold points in
the receiver. This in turn skews the time at which transitions within the signal are
recognized. Pattern Dependant Jitter (PDJ) is the result of this skew.
overlay of V1 and V2 in the region of
several key parameters.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Specification
PCI Express Base Specification Revision 1.1
SATA Revision 2.5
Figure 11-3 shows a simplified circuit model for the link. The internal blocking
.
Transmitter
+
–
Figure 11-3: Simplified Link Circuit Model
11-4).
V1
V2
Figure 11-4: Baseline Wander and PDJ
www.xilinx.com
C
IN
TXP RXP
+ +
V1 V2
C
– –
IN
TXN RXN
PDJ
Figure 11-4 where the jitter is greatest and shows
Required Range
75 to 200 nF
0 to 12 nF
"RX Termination and
Receiver
+
R
TERM
V
REF
R
TERM
–
UG196_c11_03_091906
UG196_c11_04_091906
Figure 11-5
Coupling
VTH
VTH
shows an
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