Xilinx Virtex-5 RocketIO GTP User Manual page 103

R
Table 6-6: Buffering and Phase-Alignment Trade-Offs
The TX phase-alignment circuit can also be used to minimize skew between GTP
transceivers.
aligning the PMACLK domains of multiple GTP transceivers to a common clock.
Figure 6-11
clock. Before phase alignment, all PMACLKs have an arbitrary phase difference, but after
alignment, the only phase difference is the skew for the common clock, and all data is
transmitted simultaneously as long as the datapath latency is matched.
.
When oversampling is enabled (OVERSAMPLE_MODE = TRUE), the TX buffer is used for
bit interpolation and must always be active. See
information about built-in 5x oversampling.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
The TX buffer is used when possible.
It is robust and easy to operate.
Ease of Use
If low latency is critical, the TX buffer
Latency
must be bypassed.
TX buffers offer no benefit for skew
reduction.
Skew Reduction
The TX buffer is required for
Oversampling
oversampling.
Figure 6-11 shows how the phase-alignment circuit can reduce lane skew by
shows multiple lanes running before and after phase alignment to a common
Skew
Before
Phase Alignment
Figure 6-11: Phase-Alignment Detail
www.xilinx.com
TX Buffering, Phase Alignment, and Buffer Bypass
TX Buffer
Phase alignment requires extra
logic and additional constraints on
clock sources. TXOUTCLK cannot
be used.
Phase alignment uses fewer
registers in the datapath.
The phase-alignment circuit can be
used to reduce the skew between
separate GTP transceivers. All
GTP transceivers involved must
use the same line rate.
GTP TX
Reduced
Skew
Parallel
Clocks Are
Independent
GTP TX
"Oversampling," page 143
TX Phase Alignment
GTP TX
Parallel Clocks
Are Phase Aligned to
the Same Clock Edge
GTP TX
After
Phase Alignment
UG196_c6_11_080806
for more
103