Example - Xilinx Virtex-5 RocketIO GTP User Manual

R

Example

The example system shown in
clocks. It demonstrates several different clocking schemes.
Table F-2
clock 1 as the CLKIN source, set the REFCLK_SEL to 1x1.
Table F-2: GTP Tile Utilization
GTP_DUAL
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
GTP_DUAL Tile
Clock
CLKIN
Muxing
A PLL
GTP_DUAL Tile
Clock
CLKIN
Muxing
B PLL
GTP_DUAL Tile
Clock
CLKIN
Muxing
C PLL
GTP_DUAL Tile
Clock
CLKIN
Muxing
D PLL
GTP_DUAL Tile
Clock
CLKIN
Muxing
E PLL
GTP_DUAL Tile
Clock
CLKIN
Muxing
F PLL
describes the example in
CLKIN
REFCLK_SEL
Tile Options
Clock 2
A
Clock 4
Clock 2
B
Clock 3
www.xilinx.com
Figure F-2 has six GTP_DUAL tiles with four reference
Clock 4 = GREFCLK
BUFG/BUFR
GREFCLK
BUFG/BUFR
GREFCLK
BUFG/BUFR
GREFCLK
BUFG/BUFR
GREFCLK
BUFG/BUFR
GREFCLK
BUFG/BUFR
GREFCLK
Figure F-2: Example System
Figure F-2. When using the GTP_DUAL tile D, to select
CLKNORTH_SEL
Don't Care: Nowhere to
1x1
send the northbound
xx0
clock.
1x1
0: Forward clock 2
northbound to tile A.
011
Example
IBUFDS
CLKP
GTP
Dedicated
Clock
Routing
CLKN
IBUFDS
CLKP
GTP
Dedicated
Clock
Routing
CLKN
IBUFDS
CLKP
GTP
Dedicated
Clock
Routing
CLKN
IBUFDS
CLKP
GTP
Dedicated
Clock
Routing
CLKN
IBUFDS
CLKP
GTP
Dedicated
Clock
Routing
CLKN
IBUFDS
CLKP
GTP
Dedicated
Clock
Routing
CLKN
UG196_af_02_042807
CLKSOUTH_SEL
Don't Care: No
southbound clock to
forward.
1: Drive clock 3
southbound to tile C.
Clock 3
Clock 2
Clock 1
315