Xilinx Virtex-5 RocketIO GTP User Manual page 30

Chapter 1: Introduction to the RocketIO GTP Transceiver
Table 1-3: GTP_DUAL Port Summary (Continued)
Port
TXDATA0
TXDATA1
TXDATAWIDTH0
TXDATAWIDTH1
TXDETECTRX0
TXDETECTRX1
TXDIFFCTRL0[2:0]
TXDIFFCTRL1[2:0]
TXELECIDLE0
TXELECIDLE1
TXENC8B10BUSE0
TXENC8B10BUSE1
TXENPMAPHASEALIGN
TXENPRBSTST0[1:0]
TXENPRBSTST1[1:0]
TXINHIBIT0
TXINHIBIT1
TXKERR0[1:0]
TXKERR1[1:0]
TXOUTCLK0
TXOUTCLK1
TXPMASETPHASE
TXPOLARITY0
TXPOLARITY1
30
Dir Domain
In TXUSRCLK2 Transmitting data bus.
In TXUSRCLK2 Selects the width of the TXDATA port.
Activates the receiver detection feature
In TXUSRCLK2
for PCI Express.
Controls the transmitter differential
In Async
output swing.
Drives TXN and TXP to the same
In TXUSRCLK2 voltage to perform PCI Express
electrical idle/beaconing.
In TXUSRCLK2 Enables the 8B/10B encoder.
Allows both GTP transceivers in a
GTP_DUAL tile to align their XCLKs
with their TXUSRCLKs, allowing their
In Async
TX buffers to be bypassed, and allows
the XCLKs in multiple GTPs to be
synchronized.
Transmitter test pattern generation
In TXUSRCLK2
control.
In TXUSRCLK2 Inhibits data transmission.
Indicates if an invalid code for a K
Out TXUSRCLK2
character was specified.
Provides a parallel clock generated by
the internal dividers of the GTP
transceiver.
Note:
Out N/A
duty cycle is 60/40 instead of 50/50.
TXOUTCLK cannot drive TXUSRCLK
when the TX phase-alignment circuit is
used.
Aligns XCLK with TXUSRCLK for both
In Async GTP transceivers in the GTP_DUAL
tile.
Specifies if the final transmitter output
In TXUSRCLK2
is inverted.
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Description
When INTDATAWIDTH = 1, the
Virtex-5 RocketIO GTP Transceiver User Guide
R
Section (Page)
FPGA TX Interface
(page 90)
FPGA TX Interface
(page 90)
Power Control
(page 81), PCI Express
Receive Detect Support
(page 117)
Configurable TX Driver
(page 113)
Power Control
(page 81), TX
OOB/Beacon Signaling
(page 119)
Configurable 8B/10B
Encoder (page 100),
FPGA TX Interface
(page 90)
TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)
TX PRBS Generator
(page 109)
Configurable 8B/10B
Encoder (page 100)
FPGA TX Interface
(page 91), TX Buffering,
Phase Alignment, and
Buffer Bypass (page 104)
TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)
TX Polarity Control
(page 108)
UG196 (v1.3) May 25, 2007