Configurable Clock Correction; Overview - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 7: GTP Receiver (RX)

Configurable Clock Correction

Overview

The RX elastic buffer has an additional benefit: it can tolerate frequency differences
between the XCLK and RXUSRCLK domains by performing clock correction. Clock
correction actively prevents the RX elastic buffer from getting too full or too empty by
deleting or replicating special idle characters in the data stream.
Figure 7-25
Clock correction should be used whenever there is a frequency difference between XCLK
and RXUSRCLK. It can be avoided by using the same frequency source for TX and RX, or
by using the recovered clock to drive RXUSRCLK. The
and Phase Alignment"
is not used.
168
shows a conceptual view of clock correction.
Read
RXUSRCLK
Repeatable Sequence
Read
Repeatable Sequence
Buffer More Than Half Full (Filling Up)
Figure 7-25: Clock Correction
section has more details about the steps required if clock correction
www.xilinx.com
"Nominal" Condition: Buffer Half Full
Read Write
Buffer Less Than Half Full (Emptying)
Virtex-5 RocketIO GTP Transceiver User Guide
Write
XCLK
Write
UG196_c7_22_092606
"Configurable RX Elastic Buffer
UG196 (v1.3) May 25, 2007
R