Oversampling; Overview; Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

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Oversampling

Overview

Each GTP transceiver includes built-in 5x oversampling to enable serial rates from
100 Mb/s to 500 Mb/s. At these low rates, the regular CDR must operate at 5x the desired
line rate to stay within its operating limits.
The digital oversampling circuit takes parallel data from the SIPO at 5x the desired line rate
and uses the position of bit value transitions to recover a clock. The transition points are
also used to pick an optimal sampling point to recover 2 bits of data from each set of 10 bits
presented.

Ports and Attributes

Table 7-15
Table 7-15: RX DCDR Ports
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Rx
EQ
Rx
SIPO
CDR
Rx
OOB
Shared
PMA
PLL
Divider
RX-PMA
- Set to operate at 5x desired line rate
- Datapath is automatically set to 10 bits wide
Figure 7-8: GTP RX Block Diagram
defines the ports for built-in digital oversampling.
Port
RXENSAMPLEALIGN0
RXENSAMPLEALIGN1
RXOVERSAMPLEERR0
RXOVERSAMPLEERR1
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Over- RX
sampling Polarity
RX-PCS
- Takes data from 10-bit datapath at 5x line rate
- Recovers clock at correct rate using digital algorithm
- Recovers data at the desired rate by extracting 2 bits for each 10
- Remaining datapath uses width selected by INTDATAWIDTH
Dir Clock Domain
When High, the 5X oversampler in the
PCS continually adjusts its sample point.
In RXUSRCLK2
When Low, it samples only at the point
that was active before the port went Low.
When High, indicates the FIFO in
oversampling circuit has either
Out RXUSRCLK2
overflowed or underflowed. PCS must be
reset to resume proper operation.
Oversampling
UG196_c7_08_092606
Description
143