Clocking - Xilinx Virtex-5 RocketIO GTP User Manual

Appendix A: MGT to GTP Transceiver Design Migration
Table A-1: Transceivers per Device (Continued)
Notes:
1. Because two GTP transceivers use shared PLL resources in a GTP_DUAL tile, applications where

Clocking

Virtex devices provide several available clock inputs.
family and their respective serial speeds.
Table A-2: Available Clock Inputs
Clock Differential
Family
Names (Internal)
BREFCLK
Virtex-II
BREFCLK2
Pro
REFCLK
FPGA
REFCLK2
GREFCLK
Virtex-4
REFCLK1
FPGA
REFCLK2
GREFCLK
Virtex-5
FPGA
REFCLK
Notes:
1. Nominal values. Refer to the specific data sheet for the exact values.
2. Dynamic selection between the REFCLKs or the BREFCLKs. To switch from REFCLK to BREFCLK or vice versa requires
reconfiguration.
3. BREFCLK should use dedicated GCLK I/O, which decreases GCLK I/O resources for other logic (also two pins per clock).
4. Reference clock switching is done via an attribute and the DRP using the RXAPMACLKSEL, RXBPMACLKSEL, and
TXABPMACLKSEL attributes. These attributes are located at DRP address 0x5D on bits [13:12], [11:10], and [9:8], respectively.
5. GREFCLK comes from the global clock tree and can come from any FPGA clock input. It should only be used for serial rates under
1.0 Gb/s.
Clock selection changed slightly across the first three generations of MGTs. In contrast, the
GTP_DUAL tile significantly enhances clocking capabilities by adding dedicated clocks
routing and MUXing resources.
each device.
258
Virtex Device
Virtex-5 FPGA (1)
transceivers do not have common clock settings may not be able to use both transceivers in a tile. This
will reduce the total number of available transceivers in these applications.
Dedicated Max Serial
Routes Speeds (Gb/s)
Yes
Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
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8, 12, 16, 24
Package
Dynamic
Input Voltage
Switching
(2)
3.125 Yes
(2)
3.125 Yes
(2)
2.5 Yes
(2)
2.5 Yes
(4)
1.0 Yes
(4)
6.5 Yes
(4)
6.5 Yes
Yes
3.125 Yes
Figure A-1 shows how the reference clocks are selected for
Virtex-5 RocketIO GTP Transceiver User Guide
# of Transceivers
Table A-2 shows the clocks for each
Inputs per Clocks per
Device
(1)
(V)
(3)
2.5 8
(3)
2.5 8
(3)
2.5 8
(3)
2.5 8
Note 5
8
8
1 per
GTP_DUAL GTP_DUAL
tile
1 per
GTP_DUAL GTP_DUAL
tile
UG196 (v1.3) May 25, 2007
R
Device
(3)
2
(3)
2
(3)
2
(3)
2
Note 5
4
4
1 per
tile
1 per
tile