Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 7: GTP Receiver (RX)
The elastic buffer is also used for clock correction (see
page
page
frequency matched.
require clock correction.
Table 7-27: Common Clock Configurations

Ports and Attributes

Table 7-28
Table 7-28: RX Elastic Buffer and Phase-Alignment Ports
Port Dir
INTDATAWIDTH
RXBUFRESET0
RXBUFRESET1
RXBUFSTATUS0[2:0]
Out
RXBUFSTATUS1[2:0]
RXPMASETPHASE0
RXPMASETPHASE1
Notes:
1. If an RX buffer overflow or an RX buffer underflow condition occurs, the content of the RX buffer becomes invalid, and the RX
buffer needs re-initialization by asserting RXBUFRESET.
162
168) and channel bonding (see
175). Clock correction is used in cases where PMACLK and RXUSRCLK are not
Table 7-27
Synchronous System (both sides use same physical
oscillator for REFCLK)
Separate Reference Clocks, RX uses RXRECCLK
Separate Reference Clocks, RX uses Local Clock
defines the RX elastic buffer and phase-alignment ports.
Clock
Domain
Specifies the width of the internal datapath for the entire GTP_DUAL
tile.
In Async
0: Internal datapath is 8 bits wide
1: Internal datapath is 10 bits wide
In Async Resets the RX buffer logic and re-initializes the RX buffer.
Indicates the status of the RX buffer as follows:
000: Nominal condition
001: Number of bytes in buffer are less than CLK_COR_MIN_LAT
RXUSRCLK2
010: Number of bytes in buffer are greater than
CLK_COR_MAX_LAT
101: RX Buffer Overflow
110: RX Buffer Underflow
Used to align the XCLK and RXUSRCLK domains when RXUSRCLK
In RXUSRCLK2
is driven by RXRECCLK. Allows the RXFIFO to be bypassed.
www.xilinx.com
"Configurable Clock Correction,"
"Configurable Channel Bonding (Lane Deskew),"
lists common clock configurations and shows whether they
Description
(1)
(1)
Virtex-5 RocketIO GTP Transceiver User Guide
Needs Clock Correction?
No
No
Yes
UG196 (v1.3) May 25, 2007
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