Chapter 4: Receiver - Xilinx Virtex UltraScale+ FPGAs User Manual

Receiver
This section shows how to configure and use each of the functional blocks inside the receiver
(RX). Each GTM transceiver includes an independent receiver made up of a PCS and PMA. The
following figure shows the blocks of the GTM transceiver RX. High-speed serial data flows from
traces on the board into the PMA of the GTM transceiver RX, into the PCS, and finally into the
interconnect logic.
DFE/
RX EQ ADC
FFE
The key elements within the GTM transceiver RX are:
1. RX Analog Front End
2. RX Equalizer
3. RX CDR
4. RX Fabric Clock Output Control
5. RX Margin Analysis
6. RX Pre-Coder
7. RX Gray Encoder
8. RX Polarity Control
9. RX Pattern Checker
10. RX Buffer
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
GTM Transciever RX Block Diagram
Figure 36:
To RX Parallel Data
(Near-End PCS Loopback)
Pre-
Coder
SIPO
RX PMA
RX PCS
Gray
Polarity
Encoder
PRBS
Checker
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Chapter 4: Receiver

Chapter 4
From RX Parallel Data
(Far-End PCS Loopback)
FIFO FEC
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RX
Interface
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