Xilinx Virtex-5 RocketIO GTP User Manual page 185

R
is 0, and one half the rate of RXUSRCLK when RXDATAWIDTH is 1.
how to calculate the required rate for RXUSRCLK2.
There are some rules about the relationships between clocks that must be observed for
RXUSRCLK, RXUSRCLK2, and CLKIN.
First, RXUSRCLK and RXUSRCLK2 must be positive edge aligned, with as little skew as
possible between them. As a result, low-skew clock resources (BUFGs and BUFRs) should
be used to drive RXUSRCLK and RXUSRCLK2. When the two are the same frequency, the
same clock resource is used to drive both. When the two are different frequencies,
RXUSRCLK is divided to get RXUSRCLK2. The designer must ensure that the two are
positive edge aligned.
If the channel is configured so the same oscillator drives the reference clock for the
transmitter and the receiver, REFCLKOUT or TXOUTCLK can be used to drive
RXUSRCLK and RXUSRCLK2 in the same way as they are used to drive TXUSRCLK and
TXUSRCLK2. When clock correction is turned off, RX phase alignment must be used to
align the serial clock and the parallel clocks. See
Alignment," page 161
If separate oscillators are driving the reference clocks for the transmitter and receiver on
the channel, and clock correction is not used, RXUSRCLK and RXUSRCLK2 must be
driven by RXRECCLK, and the phase-alignment circuit must be used.
If clock correction is used, RXUSRCLK and RXUSRCLK2 can be sourced by RXRECCLK,
REFCLKOUT, or TXOUTCLK.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
RXUSRCLK2 Rate
= -------------------------------------------------------------------------------------------------------------------- -
Internal Datapath Width
for details about enabling phase alignment.
www.xilinx.com
Line Rate
×
Bytes in Interface
"Configurable RX Elastic Buffer and Phase
FPGA RX Interface
Equation 7-8 shows
Equation 7-8
185