Rxrecclk; Clock Dependency; Data Path Latency - Xilinx RocketIO User Manual

Clocking

RXRECCLK

RXRECCLK is a recovered clock derived by dividing by 20 the received data stream bit rate
(whether full-rate or half-rate). If clock correction is bypassed, it is not possible to compensate for
differences in the clock embedded in the received data and the REFCLK-created USRCLKs. In this
case, RXRECCLK is used to generate the RXUSRCLKs, as shown in
RXRECCLK changes monotonically when it changes from being locked to the reference clock to
being locked to data and vice versa. The recovered bit clock jumps by a maximum of 1/16th of a bit
period every eight RXRECCLK cycles (20 ps for a data rate of 3.125 Gb/s with a 320-ps bit period)
in the interpolator. RXRECCLK is derived from this bit clock through a divide-by-20 process.
When the data input is kept static, however, the recovered clock does not frequency-lock to the
reference clock exactly, but can deviate from it by up to 400 ppm.

Clock Dependency

All signals used by the FPGA fabric to interact between user logic and the transceiver depend on an
edge of USRCLK2. These signals all have setup and hold times with respect to this clock. For
specific timing values, see Module 3 of the Virtex-II Pro data sheet. The timing relationships are
further discussed and illustrated in

Data Path Latency

With the many configurations of the MGT, the both transmit and receive data path latencies vary.
Below are several tables that provide approximate latencies for common configurations.
Table 2-6: Latency through Various Transmitter Components/Processes
Component/Process
TX Fabric/GT Interface
included
TX CRC
bypassed
included
8B/10B Encoder
bypassed
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
IBUFGDS
REFCLK_P
REFCLK_N
Figure 2-11: Using RXRECCLK to Generate RXUSRCLK and RXUSRCLK2
Note:
Bypassing the RX elastic buffer is not recommended, as the skew created by the DCM
and routing to global clock resources is uncertain and may cause unreliable performance.
1 Byte Data Path:
2.5 TXUSRCLK2 cycles
1.25 TXUSRCLK cycles
7 TXUSRCLK cycles
1 TXUSRCLK cycle
1 TXUSRCLK cycle
1 TXUSRCLK cycle
www.xilinx.com
1-800-255-7778
DCM
BUFG
CLKIN CLK0
CLKFB
RST
Appendix A, "RocketIO Transceiver Timing Model."
Latency
2 Byte Data Path:
1 TXUSRCLK2 cycle
1 TXUSRCLK cycle
Figure 2-11.
0
REFCLKSEL
REFCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
BUFG
RXRECCLK
UG024_38_112202
4 Byte Data Path:
1.25 TXUSRCLK2 cycles
2.5 TXUSRCLK cycles
R
57