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R
CLKIN
PLL_DIVSEL_REF
/[1,2]
Notes:
1. When INTDATAWIDTH = 0, PLL_DIVSEL_FB can only be set to 1, 2, or 4.
Table 5-3
values shown in
Virtex-5 Data Sheet.
Table 5-3: Communication Standards
TX/RX
Line
USRCLK
Standard
Rate
Frequency
[Gb/s]
INTDATAWIDTH = 1 (10-bit internal datapath) → (DIV = 5)
FC2
2.125
FC1
1.0625
XAUI
3.125
10G BASE-CX4
3.125
GigE
1.25
3.125
Aurora
2.5
1.25
3.125
Serial RapidIO
2.5
1.25
SATA II
3
SATA I
1.5
SAS II
3
SAS I
1.5
PCI Express
2.5
Infiniband
2.5
(4)
HD-SDI
1.485
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Phase/
Frequency
Detector
(PFD)
PLL_DIVSEL_FB
/[1,2,3,4,5]
Note 1
Figure 5-2: Shared PLL Conceptual View
shows example settings for several standard protocols. The PLL clock frequency
Table 5-3
Reference
Clock
PLL Clock
Frequency
Frequency
REFCLK
[GHz]
[MHz]
[MHz]
212.5
212.5
1.0625
106.25
106.25
1.0625
312.5
156.25
1.5625
312.5
156.25
1.5625
125
125
1.25
312.5
156.25
1.5625
250
125
1.25
125
125
1.25
312.5
156.25
1.5625
250
125
1.25
125
125
1.25
300
150
1.5
150
150
1.5
300
150
1.5
150
150
1.5
250
100
1.25
250
125
1.25
148.5
148.5
1.485
www.xilinx.com
Charge
Loop
Pump
Filter F(s)
DIV
/[4,5]
are in the operation range of the shared PLL specified in the
Reference Clock
Feedback Loop
Divider Setting
Divider Setting
PLL_DIVSEL_REF
PLL_DIVSEL_FB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
Shared PMA PLL
REFCLKOUT
PLL Clock
VCO
UG196_c5_02_041907
Divider Settings
PLL_RXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_OUT_(0/1)
PLL_TXDIVSEL_COMM_OUT
1
1
2
2
2
1
2
1
2
2
2
1
2
1
2
2
2
1
2
1
2
2
2
1
2
2
2
1
2
2
5
1
2
1
4
2
(1)
63
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