Xilinx Virtex-5 RocketIO GTP User Manual page 203

R
Figure 10-2
112_MGTREFCLKN P3
112_MGTREFCLKP P4
112_MGTRX0N P1
112_MGTRX0P N1
112_MGTRX1N R1
112_MGTRX1P T1
112_MGTTX0N N2
112_MGTTX0P M2
112_MGTTX1N T2
112_MGTTX1P U2
Figure 10-2: RREF Resistor Schematic Design Perspective
The Virtex-5 Data Sheet provides the required exact voltage level and tolerance ranges of
these analog supplies. Adequate filtering must be provided as illustrated in
Xilinx recommends the use of separate (adjustable) voltage regulators for each supply
circuit until full characterization results are available.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
MGTAVTTTX
RREF
External 50 Ω
Precision (1%)
Resistor
Figure 10-1: Resistor Calibration Circuit
illustrates the view from the schematic design perspective.
MGTREFCLKN_112
FF1136
MGTREFCLKP_112
BANK 112
MGTRXN0_112
MGTRXP0_112
MGTRXN1_112
MGTRXP1_112
MGTTXN0_112
MGTTXP0_112
MGTTXN1_112
MGTTXP1_112
Note:
The voltage levels in
portion of the Virtex-5 Data Sheet for the exact values based on operating conditions, especially
voltage and temperature.
www.xilinx.com
MGTRREF
Package Pin
U1
T3
MGTAVCCPLL_112
N3
MGTAVTTRX_112
M3
MGTAVTTTX1_112
U3
MGTAVTTTX2_112
V4
MGTRREF_112
MGTAVCC1_112 R3
MGTAVCC2_112
R4
Figure 10-3 are nominal values! Refer to the GTP transceiver
Analog Design Guidelines
Internal Resistor
Network
UG196_c10_01_110206
112_MGTVTTTX
R135
49.9
1%
1/10W
112_MGTAVCC_PLL
112_MGTVTTRX
112_MGTVTTTX
112_MGTAVCC
UG196_c10_02_110706
Figure 10-3.
203