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Ports and Attributes
Table 5-6
Table 5-6: Shared Tile Reset Ports
Port
GTPRESET
RESETDONE0
RESETDONE1
RXBUFRESET0
RXBUFRESET1
RXCDRRESET0
RXCDRRESET1
RXELECIDLERESET0
RXELECIDLERESET1
RXENELECIDLERESETB
RXRESET0
RXRESET1
TXRESET0
TXRESET1
PRBSCNTRESET
PLLPOWERDOWN
There are no attributes in this section.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
defines the shared tile reset ports.
Dir
Domain
This port is driven High to start the full GTP_DUAL reset sequence.
This sequence takes about 160 μs to complete, and systematically
In
Async
resets all subcomponents of the GTP_DUAL tile.
This port goes High when the GTP transceiver has finished reset
and is ready for use. For this signal to work correctly, CLKIN and
Out
Async
all clock inputs on the individual GTP transceiver (TXUSRCLK,
TXUSRCLK2, RXUSRCLK, RXUSRCLK2) must be driven.
In
Async
This active-High signal resets the RX buffer logic.
Individual reset signal for the RX CDR and the RX part of the PCS
In
RXUSRCLK2
for this channel. This signal is driven High to cause the CDR to give
up its current lock and return to the shared PLL frequency.
These active-High reset inputs reset the GTP transceiver receive
logic when the link is in a powerdown state.
In
Async
these signals are connected. If the link idle reset is not supported,
these signals are strapped Low.
When asserted, this active-Low signal enables the
RXELECIDLERESET0/1 inputs.
In
Async
connected when the link idle reset is supported. If
RXELECIDLERESET0/1 are not used, this signal is strapped High.
In
Async
Active-High reset for the RX PCS logic.
Resets the PCS of the GTP transmitter, including the phase adjust
In
Async
FIFO, the 8B/10B encoder, and the FPGA TX interface.
In
RXUSRCLK2 Resets the PRBS error counter.
Powers down the shared PMA PLL. Driving PLLPOWERDOWN
In
Async
from Low to High triggers a GTPRESET.
www.xilinx.com
Description
Figure 5-9
Figure 5-9
shows how this signal is
Reset
shows how
73
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