Xilinx Virtex-5 RocketIO GTP User Manual page 314

Appendix F: Advanced Clocking
All the MUX selectors reside in address 0x04 of the DRP and are mapped as shown in
Table
Table F-1: MUX Selector
To ensure that other attributes in DRP address 0x04 are not accidentally changed, use a
read/modify/write procedure to change the MUX selectors.
314
GTP_DUAL Tile
CLKIN
A PLL
Global Clock
(GREFCLK)
REFCLK_SEL
XX0
001
CLKIN
011
1X1
CLKSOUTH_SEL
Figure F-1: Reference Clock Multiplexing Stucture
F-1.
REFCLK_SEL
REFCLK_SEL[0]
REFCLK_SEL[1]
REFCLK_SEL[2]
CLKSOUTH_SEL
CLKNORTH_SEL
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BUFG/BUFR
GREFCLK
Clock
Muxing
CLKOUTNORTH
CLKINSOUTH
CLKNORTH_SEL
1 0
CLKOUTSOUTH
Bit Address
6
0x04
5
0x04
4
0x04
7
0x04
8
0x04
Virtex-5 RocketIO GTP Transceiver User Guide
IBUFDS
GTP
Dedicated
Clock
Routing
1 0
CLKP
CLKN
CLKINNORTH
UG196_af_01_032307
UG196 (v1.3) May 25, 2007
R
CLKP
CLKN