ST STM32L4+ Series Reference Manual page 2161

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56.15.36 OTG device control register (OTG_DCTL)

Address offset: 0x804

Reset value: 0x0000 0002

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 DSBESLRJCT: Deep sleep BESL reject

Bits 17:12 Reserved, must be kept at reset value.

Bit 11 POPRGDNE: Power-on programming done

Bit 10 CGONAK: Clear global OUT NAK

Bit 9 SGONAK: Set global OUT NAK

Bit 8 CGINAK: Clear global IN NAK

Bit 7 SGINAK: Set global IN NAK

Bits 6:4 TCTL[2:0]: Test control

Core rejects LPM request with BESL value greater than BESL threshold programmed.

NYET response is sent for LPM tokens with BESL value greater than BESL threshold. By

default, the deep sleep BESL reject feature is disabled.

The application uses this bit to indicate that register programming is completed after a

wakeup from power down mode.

Writing 1 to this field clears the Global OUT NAK.

Writing 1 to this field sets the Global OUT NAK.

The application uses this bit to send a NAK handshake on all OUT endpoints.

The application must set the this bit only after making sure that the Global OUT NAK

effective bit in the core interrupt register (GONAKEFF bit in OTG_GINTSTS) is cleared.

Writing 1 to this field clears the Global IN NAK.

Writing 1 to this field sets the Global non-periodic IN NAK.The application uses this bit to

send a NAK handshake on all non-periodic IN endpoints.

The application must set this bit only after making sure that the Global IN NAK effective bit

in the core interrupt register (GINAKEFF bit in OTG_GINTSTS) is cleared.

000: Test mode disabled

001: Test_J mode

010: Test_K mode

011: Test_SE0_NAK mode

100: Test_Packet mode

101: Test_Force_Enable

Others: Reserved

USB on-the-go full-speed (OTG_FS)

RM0432 Rev 6

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