ST STM32L4+ Series Reference Manual page 2167

RM0432
56.15.41 OTG all endpoints interrupt mask register
(OTG_DAINTMSK)
Address offset: 0x81C
Reset value: 0x0000 0000
The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt
the application when an event occurs on a device endpoint. However, the OTG_DAINT
register bit corresponding to that interrupt is still set.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:16 OEPM[15:0]: OUT EP interrupt mask bits
Bits 15:0 IEPM[15:0]: IN EP interrupt mask bits
56.15.42 OTG device V
(OTG_DVBUSDIS)
Address offset: 0x0828
Reset value: 0x0000 17D7
This register specifies the V
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
One per OUT endpoint:
Bit 16 for OUT EP 0, bit 19 for OUT EP 3
0: Masked interrupt
1: Unmasked interrupt
One bit per IN endpoint:
Bit 0 for IN EP 0, bit 3 for IN EP 3
0: Masked interrupt
1: Unmasked interrupt
discharge time register
BUS
BUS
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
USB on-the-go full-speed (OTG_FS)
24 23 22
OEPM[15:0]
rw rw rw
8 7 6
IEPM[15:0]
rw rw rw
discharge time after V
24 23 22
Res. Res. Res.
8 7 6
VBUSDT[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
pulsing during SRP.
BUS
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
rw rw
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