ST STM32L4+ Series Reference Manual page 2168

USB on-the-go full-speed (OTG_FS)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 VBUSDT[15:0]: Device V
56.15.43 OTG device V
(OTG_DVBUSPULSE)
Address offset: 0x082C
Reset value: 0x0000 05B8
This register specifies the V
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DVBUSP[15:0]: Device V
56.15.44 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK)
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation
(TXFE_OTG_DIEPINTx).
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
2168/2301
BUS
Specifies the V discharge time after V
BUS
V discharge time in PHY clocks / 1 024
BUS
Depending on your V
BUS
pulsing time register
BUS
BUS
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
BUS
Specifies the V pulsing time during SRP. This value equals:
BUS
V pulsing time in PHY clocks / 1 024
BUS
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
discharge time
pulsing during SRP. This value equals:
BUS
load, this value may need adjusting.
pulsing time during SRP.
24 23 22
Res. Res. Res.
8 7 6
DVBUSP[15:0]
rw rw rw
pulsing time. This feature is only relevant to OTG1.3.
24 23 22
Res. Res. Res.
8 7 6
INEPTXFEM[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RM0432
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
rw rw