Motorola MPC533 Reference Manual page 615

15.4.5 QSPI Interrupt Generation
15.4.6 QSMCM Configuration Register (QSMCMMCR)
The QSMCMMCR contains parameters for interfacing to the CPU and the intermodule
bus. This register can be modified only when the CPU is in supervisor mode.
MSB 1
0
Field STOP FRZ1
SRESET 0 0
Addr
Figure 15-4. QSMCM Configuration Register (QSMCMMCR)
Bits Name
0 STOP
1 FRZ1
2:7 —
8 SUPV
9:11 —
12:15 —
15.4.7 QSMCM Test Register (QTEST)
The QTEST register is used for factory testing of the MCU.
15.4.8 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL)
The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the
QSMCM. The two SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI. The
QSPI uses a separate field, ILQSPI. The level value is used to determine which interrupt is
serviced first when two or more modules or external peripherals simultaneously request an
interrupt. The user can select among 32 levels. This register can be accessed only when the
CPU is in supervisor mode.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
—
00_0000
Table 15-4. QSMCMMCR Bit Descriptions
Stop enable. Refer to Section 15.4.1, "Low-Power Stop Operation."
0 Normal clock operation
1 Internal clocks stopped
Freeze1 bit. Refer to Section 15.4.2, "Freeze Operation."
0 Ignore the FREEZE signal
1 Halt the QSMCM (on transfer boundary)
Reserved
Supervisor / Unrestricted. Refer to Section 15.4.3, "Access Protection."
0 Assigned registers are unrestricted (user access allowed)
1 Assigned registers are restricted (only supervisor access allowed)
Reserved
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in QSM
implementations that use hardware interrupt arbitration.
Chapter 15. Queued Serial Multi-Channel Module
6 7 8 9
SUPV
1
0x30 5000
Description
QSMCM Global Registers
10 11 12 13
—
000_0000
14 LSB
15
15-9