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Decompressor Class Configuration Registers (DCCR0-15)
G.4
Decompressor Class Configuration Registers
(DCCR0-15)
The DCCR fields are programmed to achieve maximum flexibility in the vocabulary tables
placement into the two DECRAM banks under constraints, implied by hardware, which
are:
• A bypass field must always be in the second field of the compressed instruction
• When fetching 32 bits of decompressed instruction from the DECRAM, each 16 bits
will be read from different RAM banks.
The DCCR registers should be programmed with data supplied by the code compression
tool, in order to be correlated with the compressed code.
,
Msb
1
0
Field
TP1LEN
HRESET
16
17
18
Field
HRESET
Undefined
Addr
0x2F + A000 (DCCR0)
(DCCR5), A018 (DCCR6), A01C (DCCR7), A020 (DCCR8), A024 (DCCR9), A028 (DCCR10), A02C
(DCCR11), A030 (DCCR12), A034 (DCCR13), A038 (DCCR14), A03C (DCCR15)
Figure G-14. Decompressor Class Configuration Registers
1. The DCCR0 register is hard coded for the "bypass decompressor class." Write accesses do not affect the DCCR0
register. The DCCR0 register will always return 0x0000 0000 when read.
G-24
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
3
4
5
TP2LEN
19
20
21
TP2BA
AS
0
Undefined
1
, 0x2F + A004 (DCCR1), A008 (DCCR2), A00C (DCCR3), A010 (DCCR4), A014
MPC533 Reference Manual
6
7
8
9
Undefined
22
23
24
25
DS
10
11
12
13
TP1BA
26
27
28
29
—
0000_0000
1
(DCCR0–15)
MOTOROLA
14
15
TP2BA
30
Lsb
31
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