Motorola MPC533 Reference Manual page 399

Table 10-3. Programming Rules for Timing Strobes (continued)
Access
TRLX ACS
Type
0 write 11
1 read 00
1 read 10
1 read 11
1 write 00
1 write 10
1 write 11
1 write 00
1 write 10
1 write 11
Note: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-case
timing values. 1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
Additional timing rules not covered in Table 10-3 include the following:
• If SETA = 1, an external TA signal is required to terminate the cycle.
• If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if
SCY = 0000)
• If TRLX = 1, the number of wait states = 2 ∗ SCY & 2 ∗ BSCY
• ACS = 01 is not defined (reserved).
• If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a
following read cycle to another region, or between a read cycle and a following write
cycle to any region.
• If LBDIP = 1 (late BDIP assertion), the BDIP signal is asserted only after the
number of wait states for the first beat in a burst have elapsed. See Figure 9-13 in
Chapter 9, "External Bus Interface," as well as Section 9.5.5, "Burst Mechanism."
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Address
Negated to
CSNT to CS
Add/Data
Asserted
Invalid
1 1/2 * clock 1/2 * clock
X 0 1/4 * clock
X (1 + 1/4) * 1/4 * clock
clock
X (1 + 1/2) * 1/4 * clock
clock
0 0 1/4 * clock
0 (1 + 1/4) * 1/4 * clock
clock
0 (1 + 1/2) * 1/4 * clock
clock
1 0 1/4 * clock
1 (1 + 1/4) * (1 + 1/2) *
clock clock
1 (1 + 1/2) * (1 + 1/2) *
clock clock
Chapter 10. Memory Controller
CS Address to WE/BE
WE/BE or Negated to
OE Add/Data
Asserted Invalid
3/4 * clock 1/2 * clock
3/4 clock
(1 + 3/4) *
clock
(1 + 3/4) *
clock
3/4 clock 1/4 * clock
(1 + 3/4) * 1/4 * clock
clock
(1 + 3/4) 1/4 * clock
clock
3/4 clock (1 + 1/2) *
(1 + 3/4) (1 + 1/2) *
clock
(1 + 3/4) (1 + 1/2) *
clock
Chip-Select Timing
OE
Negated to
Number of
Add/Data
Invalid
X 2 + SCY
X 1/4 * clock
2 * SCY
X 1/4 * clock
2 * SCY
X 1/4 * clock
2 * SCY
X
2 * SCY
X
2 * SCY
X
2 * SCY
X
clock 2 * SCY
X
clock 2 * SCY
X
clock 2 * SCY
Total
Cycles
2 +
3 +
3 +
2 +
3 +
3 +
3 +
4 +
4 +
10-23