Motorola MPC533 Reference Manual page 657

Table 15-25. SCCxR1 Bit Descriptions (continued)
Bits Name
11 ILIE Idle-line interrupt enable
0 SCI IDLE interrupts disabled.
1 SCI IDLE interrupts enabled.
12 TE Transmitter enable
0 SCI transmitter disabled (TXD pin can be used as general-purpose output)
1 SCI transmitter enabled (TXD pin dedicated to SCI transmitter).
13 RE Receiver Enable
0 SCI receiver disabled (RXD pin can be used as general-purpose input).
1 SCI receiver enabled (RXD pin is dedicated to SCI receiver).
14 RWU Receiver wakeup. Refer to Section 15.7.7.10, "Receiver Wake-Up."
0 Normal receiver operation (received data recognized).
1 Wakeup mode enabled (received data ignored until receiver is awakened).
15 SBK Send break
0 Normal operation.
1 Break frame(s) transmitted after completion of current frame.
15.7.4 SCI Status Register (SCxSR)
SCxSR contains flags that show SCI operating conditions. These flags are cleared either by
SCIx hardware or by a read/write sequence. The sequence consists of reading the SCxSR
(either the upper byte, lower byte, or the entire half-word) with a flag bit set, then reading
(or writing, in the case of flags TDRE and TC) the SCxDR (either the lower byte or the
half-word).
The contents of the two 16-bit registers SCxSR and SCxDR appear as upper and lower
half-words, respectively, when the SCxSR is read into a 32-bit register. An upper byte
access of SCxSR is meaningful only for reads. Note that a word read can simultaneously
access both registers SCxSR and SCxDR. This action clears the receive status flag bits that
were set at the time of the read, but does not clear the TDRE or TC flags. To clear TC, the
SCxSR read must be followed by a write to register SCxDR (either the lower byte or the
half-word). The TDRE flag in the status register is read-only.
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted
status bits but before the CPU has read or written the SCxDR, the newly set status bit is not
cleared. Instead, SCxSR must be read again with the bit set and SCxDR must be read or
written before the status bit is cleared.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 15. Queued Serial Multi-Channel Module
Serial Communication Interface
Description
15-51