Motorola MPC533 Reference Manual page 324

Bus Operations
Signal Name
RETRY
9.5 Bus Operations
This section provides a functional description of the system bus, the signals that control it,
and the bus cycles provided for data transfer operations. It also describes the error
conditions, bus arbitration, and reset operation.
The MPC533 generates a system clock output (CLKOUT). This output sets the frequency
of operation for the bus interface directly. Internally, the MPC533 uses a phase-lock loop
(PLL) circuit to generate a master clock for all of the MPC533 circuitry (including the bus
interface) which is phase-locked to the CLKOUT output signal.
All signals for the MPC533 bus interface are specified with respect to the rising edge of the
external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with
respect to that edge. Since the same clock edge is referenced for driving or sampling the bus
signals, the possibility of clock skew could exist between various modules in a system due
to routing or the use of multiple clock lines. It is the responsibility of the system to handle
any such clock skew problems that could occur.
9.5.1 Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions that must occur on the MPC533
bus to perform a complete bus transaction. A simplified scheme of the basic transfer
protocol is illustrated in Figure 9-3.
Arbitration
The basic transfer protocol provides for an arbitration phase and an address and data
transfer phase. The address phase specifies the address for the transaction and the transfer
attributes that describe the transaction. The data phase performs the transfer of data (if any
is to be transferred). The data phase may transfer a single beat of data (four bytes or less)
9-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 9-1. MPC533 SIU Signals (continued)
Pins Active
1 Low
Address Transfer
Figure 9-3. Basic Transfer Protocol
MPC533 Reference Manual
I/O
In the case of regular transaction, this signal is driven
I by the slave device to indicate that the MPC533 must
relinquish the ownership of the bus and retry the cycle.
When an external master owns the bus and the
O internal MPC533 bus initiates access to the external
bus at the same time, this signal is used to cause the
external master to relinquish the bus for one clock to
solve the contention.
Data Transfer
Description
Termination
MOTOROLA