Table of Contents
Advertisement
SHIFT DR
FROM TDI
When the bypass register is selected by the current instruction, the shift register stage is set
to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the
first bit to be shifted out after selecting the bypass register will always be a logic zero.
23.1.2.4 CLAMP
The CLAMP instruction selects the single-bit bypass register as shown in Figure 23-4, and
the state of all signals driven from system output pins is completely defined by the data
previously shifted into the boundary scan register (for example, using the
SAMPLE/PRELOAD instruction).
23.1.3
HI-Z
The HI-Z instruction is provided as a manufacturer's optional public instruction to prevent
having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all
output drivers, including the two-state drivers, are turned off (i.e., high impedance). The
instruction selects the bypass register.
23.2 Restrictions
The control afforded by the output enable signals using the boundary scan register and the
EXTEST instruction requires a compatible circuit-board test environment to avoid
device-destructive configurations. The user must avoid situations in which the output
drivers are enabled into actively driven networks.
The features a low-power stop mode. The interaction of the scan chain interface with
low-power stop mode is as follows:
1. The TAP controller must be in the test-logic-reset state to either enter or remain in
the low-power stop mode. Leaving the TAP controller in the test-logic-reset state
negates the ability to achieve low-power, but does not otherwise affect device
functionality.
2. The TCK input is not blocked in low-power stop mode. To consume minimal
power, the TCK input should be externally connected to V
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
G1
0
1
Mux
1
Figure 23-4. Bypass Register
Chapter 23. IEEE 1149.1-Compliant Interface (JTAG)
D
C
CLOCK DR
Restrictions
TO TDO
or ground.
DD
23-7
Advertisement
Table of Contents
