Motorola MPC533 Reference Manual page 916

Software Monitor Debugger Support
command", The value of the first memory block address, – 4, must be written to the general
purpose register 30.
To end a download procedure, an "end download procedure" command should be issued to
the debug port, and then, additional DATA transaction should be sent by the development
tool. This data word will NOT be placed into the system memory, but it is needed to stop
the procedure gracefully.
21.5 Software Monitor Debugger Support
When in debug mode disable, a software monitor debugger can make use of all of the
development support features defined in the CPU. When debug mode is disabled all events
result in regular interrupt handling, i.e. the processor resumes execution in the
corresponding interrupt handler. The exception cause register (ECR) and the debug enable
register (DER) only influence the assertion and negation of the freeze signal.
21.5.1 Freeze Indication
The internal freeze signal is connected to all relevant internal modules. These modules can
be programmed to stop all operations in response to the assertion of the freeze signal. In
order to enable a software monitor debugger to broadcast the fact that the debug software
is now executed, it is possible to assert and negate the internal freeze signal also when
debug mode is disabled.
The assertion and negation of the freeze signal when in debug mode disable is controlled
by the exception cause register (ECR) and the debug enable register (DER) as described in
Figure 21-7. In order to assert the freeze signal the software needs to program the relevant
bits in the debug enable register (DER). In order to negate the freeze line the software needs
to read the exception cause register (ECR) in order to clear it and perform an rfi instruction.
If the exception cause register (ECR) is not cleared before the rfi is performed the freeze
signal is not negated. Therefore it is possible to nest inside a software monitor debugger
without affecting the value of the freeze line although rfi may be performed a few times.
Only before the last rfi the software needs to clear the exception cause register (ECR).
The above mechanism enables the software to accurately control the assertion and the
negation of the freeze signal.
21.6 Development Support Registers
Table 21-17 lists the registers used for development support in SPR number order, and the
register sections, Section 21.6.2, "Comparator A–D Value Registers (CMPA–CMPD)"
through Section 21.6.13, "Development Port Data Register (DPDR)," follow the same SPR
order. The registers are accessed with the mtspr and mfspr instructions.
21-46 MPC533 Reference Manual MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE