Motorola MPC533 Reference Manual page 1108

Power-Up/Down Sequencing
The first step in the sequence is required is due to gate-to-drain stress limits for transistors
in the pads of 2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Damage can occur
if gate-to-drain voltage potential is greater than 3.1 V. This is only a concern at
power-up/down. The second step in the sequence is required is due to ESD diodes in the
pad logic for dual 2.6-V/5-V compliant pins and 2.6-V pins. The diodes are forward biased
when V is greater than V
DDL
Figure K-1 illustrates the power-up sequence if no keep-alive supply is required.
Figure K-2 illustrates the power-up sequence if a keep-alive supply is required. The
keep-alive supply should be powered-up at the same instant or before both the high voltage
and low voltage supplies are powered-up.
V
DDH
V
DDH
Figure K-1. Option A Power-Up Sequence Without Keep-Alive Supply
V
DDKA
Figure K-2. Option A Power-Up Sequence With Keep-Alive Supply
The option A power-down sequence (excluding V
1. V ≤ V
DDH DDL
K-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
and will start to conduct current.
DDH
3.1-V lead
cannot lead V by more than 3.1 V
DDL
cannot lag V by more than 0.5 V
DDL
3.1-V lead
V cannot lead V by more than 3.1 V
DDH DDL
V cannot lag V by more than 0.5 V
DDH DDL
+ 3.1 V (V cannot lag V
DDH
MPC533 Reference Manual
0.5-V lag
0.5-V lag
) is
DDKA
by more than 3.1 V)
DDL
V
DDH
V
DDL
V
DDH
V
DDL
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