Implementation-Dependent Debug Exceptions - Motorola MPC533 Reference Manual

Table 3-38. Register Settings Following a Data Protection
Register Name
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Data/Storage Interrupt Status
Register (DSISR)
Data Address Register (DAR)
1
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format.
When a data protection error exception is taken, instruction execution resumes at offset
0x1400 from the base address indicated by MSR[IP].

3.15.4.16 Implementation-Dependent Debug Exceptions

Implementation-dependent debug exceptions occur in the following cases:
• When there is an internal breakpoint match (for more details, refer to Chapter 21,
"Development Support."
• When a peripheral breakpoint request is asserted to the MPC533 core.
• When the development port request is asserted to the MPC533 core. Refer to
Chapter 21, "Development Support," for details on how to generate the
development port-interrupt request.
See Table 3-39 for debug-exception register settings.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Error Exception (continued)
Bits
0:15 Cleared to 0
Other Loaded from bits [16:31] of MSR. In the current implementation,
bit 30 of the SRR1 is never cleared, except by loading a zero
value from MSR[RI]
IP No change
ME No change
LE Bit is copied from ILE
DCMPEN This bit is set according to (BBCMCR[EN_COMP] and
BBCMCR[EXC_COMP])
Other Cleared to 0
0:3 Cleared to 0
4 Set to 1 if the storage access is not permitted by the protection
mechanism. Otherwise cleared to 0
5 Cleared to 0
6 Set to 1 for a store operation and cleared to 0 for a load
operation
7:31 Cleared to 0
All Set to the effective address of the data access that caused the
exception
Chapter 3. Central Processing Unit
Operating Environment Architecture (OEA)
Description
3-63