Table of Contents
Advertisement
10.2.2
Port Size Configuration
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be accessed
as odd or even bytes. Defined 16-bit ports, when connected to data bus lines zero to 15, can
be accessed as odd bytes, even bytes, or even half-words. Defined 32-bit ports can be
accessed as odd bytes, even bytes, odd half-words, even half-words, or words on word
boundaries. The port size is specified by the PS bits in the base register.
10.2.3
Write-Protect Configuration
The WP bit in each base register can restrict write access to its range of addresses. Any
attempt to write this area results in the associated WPER bit being set in the MSTAT.
If an attempt to access an external device results in a write-protect violation, the memory
controller considers the access to be no match. No chip-select line is asserted externally,
and the memory controller does not terminate the cycle. The external bus interface
generates a normal cycle on the external bus. Since the memory controller does not
acknowledge the cycle internally, the cycle may be terminated by external logic asserting
TA or by the on-chip bus monitor asserting TEA.
10.2.4
Address and Address Space Checking
The base address is written to the BRx. The address mask bits for the address are written to
the OR. The address type access value, if desired, is written to the AT bits in the BRx. The
ATM bits in the ORx can be used to mask this value. If address type checking is not desired,
program the ATM bits to zero.
Each time an external bus cycle access is requested, the address and address type are
compared with each one of the banks. If a match is found, the attributes defined for this
bank in its BRx and ORx are used to control the memory access. If a match is found in more
than one bank, the lowest bank matched handles the memory access (e.g., bank zero is
selected over bank one).
When an external master accesses a slave on the bus, the
internal AT[0:2] lines reaching the memory controller are
forced to 100.
10.2.5
Burst Support
The memory controller supports burst accesses of external burstable memory. To enable
bursts, clear the burst inhibit (BI) bit in the appropriate base register. Burst support is for
read only.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
Chapter 10. Memory Controller
Memory Controller Architecture
10-5
Advertisement
Table of Contents
