Motorola MPC533 Reference Manual page 1043

• TP1 base address, TP2 base address = the two tables' base addresses for RAM #1
and RAM #2, respectively.
• AS, DS=0
Data brought from RAM#1 is the 16 Msbs of the decompressed instruction and data
brought from RAM#2 is the 16 Lsbs of the decompressed instruction.
G.2.9.3 Twin Segment Full Compression – CLASS_2
This instruction is divided into two segments. Each segment is compressed and mapped
into a different vocabulary. The vocabularies reside in different RAMs. Proper
programming can swap the vocabularies' locations.
Msb
16-bit segment #1 – to be compressed
Alternative #1 (CLASS_2a)
2- to 9-bit TP1 for segment #1
4-bit class
Alternative #2 (CLASS_2b)
2- to 9-bit TP1 for segment #2
4-bit class
The definition of the class includes:
• TP1 length=2-9
• TP2 length=2-9
• AS=0
• For alternative #1:
— TP1 base address = base address of segment #1 vocabulary in RAM #1
— TP2 base address = base address of segment #2 vocabulary in RAM #2
— DS=0
• For alternative #2:
— TP1 base address = base address of segment #2 vocabulary in RAM #1
— TP2 base address = base address of segment #1 vocabulary in RAM #2
— DS=1
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Uncompressed Instruction
16-bit segment #2 – to be compressed
Compressed Instruction
Figure G-8. CLASS_2 Instruction Layout
Appendix G. MPC534 Compression Features
Class-Based Compression Model Main Principles
2- to 9-bit TP2 for segment #2
2- to 9-bit TP2 for segment #1
G-11