Table of Contents
Advertisement
Development Support Registers
Table 21-28. LCTRL2 Bit Descriptions (continued)
Bits
Name
29
DLW1EN
30
SLW0EN
31
SLW1EN
Note: LCTRL2 is cleared following reset.
For each watchpoint, three control register fields (LWxIA, LWxLA, LWxLD) must be
programmed. For a watchpoint to be asserted, all three conditions must be detected.
21.6.11 I-Bus Support Control Register (ICTRL)
MSB
1
2
3
0
Field
CTA
Reset
16
17
18
19
Field IWP2
IWP3
Reset
Addr
Figure 21-24. I-Bus Support Control Register (ICTRL)
1
Changing the instruction show cycle programming starts to take effect only from the second instruction after the
actual mtspr to ICTRL.
If the processor aborts a fetch of the target of a direct branch (due to an exception), the target
is not always visible on the external pins. Program trace is not affected by this phenomenon.
21-58
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Development port trap enable selection of the 2nd L-bus watchpoint
(read only bit)
0 trap disabled (reset value)
1 trap enabled
Software trap enable selection of the 1st L-bus watchpoint
0 trap disabled (reset value)
1 trap enabled
Software trap enable selection of the 2nd L-bus watchpoint
0 trap disabled (reset value)
1 trap enabled
4
5
6
CTB
0000_0000_0000_0000
20
21
22
SIWP0
SIWP1
SIWP2
EN
EN
EN
0000_0000_0000_0000
MPC533 Reference Manual
Description
7
8
9
CTC
23
24
25
SIWP3
DIWP0
DIWP1
DIWP2
EN
EN
EN
SPR 158
10
11
12
13
CTD
IWP0
26
27
28
29
DIWP3
IFM ISCT_SER
EN
EN
MOTOROLA
14
15
IWP1
30
LSB
31
1
Advertisement
Table of Contents
