Condition Register (Cr) - Motorola MPC533 Reference Manual

Table 3-5. FPSCR Bit Descriptions (continued)
Bits Name
29 NI Non-IEEE mode bit.
30–31 RN Floating-point rounding control.
00 Round to nearest
01 Round toward zero
10 Round toward +infinity
11 Round toward -infinity
Table 3-6 illustrates the floating-point result flags that correspond to FPSCR[15:19].
Table 3-6. Floating-Point Result Flags in FPSCR
3.7.4

Condition Register (CR)

The condition register (CR) is a 32-bit register that reflects the result of certain operations
and provides a mechanism for testing and branching. The bits in the CR are grouped into
eight 4-bit fields: CR0 to CR7.
MSB 1 2 3 4
0
Field CR0
Reset
The CR fields can be set in the following ways:
• Specified fields of the CR can be set by an instruction (mtcrf) to move to the CR
from a GPR.
• Specified fields of the CR can be moved from one CRx field to another with the mcrf
instruction.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Result Flags
(Bits 15:19)
C<>=?
10001
01001
01000
11000
10010
00010
10100
00100
00101
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
CR1 CR2 CR3
Figure 3-7. Condition Register (CR)
Chapter 3. Central Processing Unit
User Instruction Set Architecture (UISA) Register Set
Description
Result Value Class
Quiet NaN
– Infinity
– Normalized number
– Denormalized number
– Zero
+ Zero
+ Denormalized number
+ Normalized number
+ Infinity
CR4
Unchanged
CR5 CR6
—
—
31
CR7
3-17