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17.4.2
Wait States
Figure 17-2.
The MIOS14 does not generate wait states.
If a supervisor privilege address space is accessed in user mode, the module returns a bus
error.
All MIOS14 unimplemented locations within the addressable range, return a logic 0 when
accessed. In addition, the internal TEA (transfer error acknowledge) signal is asserted.
All unused bits within MIOS14 registers return a 0 when accessed.
17.5 MIOS14 I/O Ports
Each signal of each submodule can be used as an input, output, or I/O port:
17.6 MIOS14 Bus Interface Submodule (MBISM)
The MIOS14 bus interface submodule (MBISM) is used as an interface between the MIOB
(modular I/O bus) and the IMB3. It allows the CPU to communicate with the MIOS14
submodules.
17.6.1
MIOS14 Bus Interface (MBISM) Registers
Table 17-3 is the address map for the MBISM submodule.
MOTOROLA
Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 17-2. MIOS14 I/O Ports
Number of Pins
Submodule
per Module
MPIOSM
16
MMCSM
2
MDASM
1
MPWMSM
1
MIOS14 I/O Ports
MIOS14 Memory Map
Type
I/O
I
I/O
I/O
17-11
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