Motorola MPC533 Reference Manual page 877

21.1.4.2 Detecting the Trace Window Start Address
When using back trace, latching the value of the status pins (VF and VFLS), and the address
of the cycles marked as program trace cycle, should start immediately after the negation of
reset. The start address is the first address in the program trace cycle buffer.
When using window trace, latching the value of the status pins (VF and VFLS), and the
address of the cycles marked as program trace cycle, should start immediately after the first
VSYNC is reported on the VF pins. The start address of the trace window should be
calculated according to first two VF pins reports.
Assuming that VF1 and VF2 are the two first VF pins reports and T1 and T2 are the two
addresses of the first two cycles marked with the program trace cycle attribute that were
latched in the trace buffer, use the following table to calculate the trace window start
address.
Table 21-4. Detecting the Trace Buffer Start Point
VF1 VF2
011 001
VSYNC sequential
011 110
VSYNC branch direct taken
011 101
VSYNC branch indirect taken
21.1.4.3 Detecting the Assertion/Negation of VSYNC
Since the VF pins are used for reporting both instruction type information and queue flush
information, the external hardware must take special care when trying to detect the
assertion/negation of VSYNC. When VF = 011 it is a VSYNC assertion/negation report
only if the previous VF pins value was one of the following values: 000, 001, or 010.
21.1.4.4 Detecting the Trace Window End Address
The information on the status pins that describes the last fetched instruction and the last
queue/history buffer flushes, changes every clock. Cycles marked as program trace cycle
are generated on the external bus only when possible (when the SIU wins the arbitration
over the external bus). Therefore, there is some delay between the information reported on
the status pins that a cycle marked as program trace cycle will be performed on the external
bus and the actual time that this cycle can be detected on the external bus.
When VSYNC is negated (through the serial interface of the development port), the CPU
delays the report of the of the assertion/negation of VSYNC on the VF pins (VF = 011) until
all addresses marked with the program trace cycle attribute were visible externally.
Therefore, the external hardware should stop sampling the value of the status pins (VF and
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Starting point
T1 VSYNC asserted followed by a sequential instruction.
The start address is T1
T1 - 4 + VSYNC asserted followed by a taken direct branch.
offset (T1 - 4) The start address is the target of the direct branch
T2 VSYNC asserted followed by a taken indirect branch.
The start address is the target of the indirect branch
Chapter 21. Development Support
Program Flow Tracking
Description
21-7