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• When executing any non-implemented instruction. This includes all illegal and
unimplemented optional instructions and all floating-point instructions.
• When executing a mtspr or mfspr instruction that specifies an un-implemented
internal-to-the-processor SPR, regardless of the value of bit 0 of the SPR.
• When executing a mtspr or mfspr that specifies an un-implemented
external-to-the-processor register and SPR0 = 0 or MSR[PR] = 0 (no program
interrupt condition).
Table 3-36 shows the register settings set when a software emulation exception occurs.
Table 3-36. Register Settings Following a Software Emulation Exception
Register Name
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
3.15.4.14 Implementation-Dependent Instruction Protection Exception
(0x1300)
The implementation-specific instruction storage protection error interrupt occurs in the
following cases:
• The fetch access violates storage protection and MSR[IR] = 1.
• The fetch access is to guarded storage and MSR[IR] = 1.
The register settings for instruction protection exceptions are shown in Table 3-37.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Bits
1
All
Set to the effective address of the instruction that caused the
interrupt
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current implementation,
bit 30 of the SRR1 is never cleared, except by loading a zero
value from MSR[RI].
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
This bit is set according to (BBCMCR[EN_COMP] and
BBCMCR[EXC_COMP])
Other
Cleared to 0
Chapter 3. Central Processing Unit
Operating Environment Architecture (OEA)
Description
3-61
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