Precise Exceptions; Exception Vector Table; Instruction Timing - Motorola MPC533 Reference Manual

Instruction Timing

3.11.4

Precise Exceptions

In the MPC533, all synchronous (instruction-caused) exceptions are precise. When a
precise exception occurs, the processor backs the machine up to the instruction causing the
exception. This ensures that the machine is in its correct architecturally-defined state. The
following conditions exist at the point a precise exception occurs:
1. Architecturally, no instruction following the faulting instruction in the code stream
has begun execution.
2. All instructions preceding the faulting instruction appear to have completed with
respect to the executing processor.
3. SRR0 addresses either the instruction causing the exception or the immediately
following instruction. Which instruction is addressed can be determined from the
exception type and the status bits.
4. Depending on the type of exception, the instruction causing the exception may not
have begun execution, may have partially completed, or may have completed
execution.
3.11.5

Exception Vector Table

The setting of the exception prefix (IP) bit in the MSR determines how exceptions are
vectored. If the bit is cleared, the exception vector table begins at the physical address
0x0000 0000; if IP is set, the exception vector table begins at the physical address 0xFFF0
0000. Table 3-21 shows the exception vector offset of the first instruction of the exception
handler routine for each exception type.
In the MPC533, the exception table can additionally be
relocated by the BBC module to internal memory and reduce
the total size required by the exception table (see Section 4.3,
"Exception Table Relocation (ETR)."
3.12 Instruction Timing
The MPC533 processor is pipelined. Because the processing of an instruction is broken into
a series of stages, an instruction does not require the entire resources of the processor.
The instruction pipeline in the MPC533 has four stages:
1. The dispatch stage is implemented using a distributed mechanism. The central
dispatch unit broadcasts the instruction to all units. In addition, scoreboard
information (regarding data dependencies) is broadcast to each execution unit. Each
execution unit decodes the instruction. If the instruction is not implemented, a
program exception is taken. If the instruction is legal and no data dependency is
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
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