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Clocks Unit Programming Model
MSB
1
0
Field
PORESET
HRESET
16
17
SPLSS TEXPS TEXP_INV TMIST — CSRC LPM CSR LOLRE —
PORESET
0
1
HRESET
U
1
Addr
Figure 8-14. PLL, Low-Power, and Reset-Control Register (PLPRCR)
Bits
Name
0:11
MF
12
—
13
LOCS
14
LOCSS
15
SPLS
8-34
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
3
4
MF
0000_0000_0000 or 0000_0000_1000
18
19
20
U
0
U
Table 8-11. PLPRCR Bit Descriptions
Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to
the phase comparator. The MF bits control the value of the divider in the SPLL feedback loop.
The phase comparator determines the phase shift between the feedback signal and the
reference clock. This difference results in either an increase or decrease in the VCO output
frequency.
The MF bits can be read and written at any time. However, this field can be write-protected
by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits
causes the SPLL to lose lock. Also, the MF field should not be modified when entering or
exiting from low power mode (LPM change), or when back-up clock is active.
The normal reset value for the DFNH bits is zero (divide by 1). When the PLL is operating in
one-to-one mode, the multiplication factor is set to x1 (MF = 0).
Reserved
Loss of clock status. When the oscillator or external clock source is not at the minimum
frequency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the oscillator
or external clock source is functioning normally. This bit is reset only on power-on reset.
Writes to this bit have no effect.
0 No loss of oscillator is currently detected
1 Loss of oscillator is currently detected
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set.
LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. The reset value is determined during hard reset. The STBUC bit will be set
provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL
is locked when HRESET is asserted.
0 No loss of oscillator has been detected
1 Loss of oscillator has been detected
System PLL lock status bit
0 SPLL is currently not locked
1 SPLL is currently locked
MPC533 Reference Manual
5
6
7
8
9
Unaffected
21
22
23
24
25
00_0000_0000_0000
000
Unaffected
0x2F C284
Description
10
11
12
13
14
— LOCS LOCSS SPLS
0000
26
27
28
29
30
DIVF
—
Unaffected
MOTOROLA
15
LSB
31
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