Branch Processing Unit (Bpu) - Motorola MPC533 Reference Manual

Table 3-1 summarizes the RCPU execution units.
Unit
Branch processing
unit (BPU)
Load/store unit (LSU) Includes implementation of all load and store instructions, whether defined as part
Integer unit (IU)
Floating-point unit
(FPU)
The following sections describe these execution units in greater detail.
3.4.1

Branch Processing Unit (BPU)

The BPU, located within the instruction sequencer, performs condition register look-ahead
operations on conditional branches. The BPU looks through the instruction queue for a
conditional branch instruction and attempts to resolve it early, achieving the effect of a
zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when it encounters an unresolved conditional branch instruction, the
processor pre-fetches instructions from the predicted target stream until the conditional
branch is resolved.
The BPU uses a calculation feature to compute branch target addresses with three
special-purpose, user-accessible registers: the link register (LR), the count register (CTR),
and the condition register (CR). The BPU calculates the return pointer for a subroutine, then
calls and saves it into the LR. The LR also contains the branch target address for the branch
conditional to link register (bclrx) instruction. The CTR contains the branch target address
for the branch conditional to count register (bcctrx) instruction. The contents of the LR and
CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather
than general-purpose or floating-point registers, execution of branch instructions is
independent from execution of integer instructions. The CR bits indicate conditions that
may result from the execution of relevant instructions.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 3-1. RCPU Execution Units
Includes the implementation of all branch instructions
of the integer processor or the floating-point processor
Includes implementation of all integer instructions except load/store instructions.
This module includes the GPRs (including GPR history and scoreboard) and the
following subunits: the IMUL-IDIV, which includes the implementation of the
integer multiply and divide instructions and the ALU-BFU, which includes
implementation of all integer logic, add and subtract instructions, and bit field
instructions.
Includes the FPRs (including FPR history and scoreboard) and the
implementation of all floating-point instructions except load and store
floating-point instructions
Chapter 3. Central Processing Unit
Independent Execution Units
Description
3-5