Motorola MPC533 Reference Manual page 374

Bus Operations
valid on the bus for one clock. The data phase must not require a transfer acknowledge to
terminate the bus show cycle.
Show cycles are activated by properly setting the SIUMCR register bits. Refer to
Section 6.2.2.1.1, "SIU Module Configuration Register (SIUMCR)." Construction
visibility is controlled by the ISCT_SER bits in the ICTRL register. Refer to Table 22-21.
Data visibility is controlled by the LSHOW bits of the L2U_MCR register. Refer to
Table 11-7.
In a burst show cycle only the first data beat is shown externally. Refer to Table 9-8 for
show cycle transaction encodings.
Instruction show cycle bus transactions have the following characteristics (see
Figure 9-41):
• One clock cycle
• Address phase only; in decompression on mode part of the compressed address is
driven on data lines together with address lines. The external bus interface adds one
clock delay between a read cycle and such show cycle.
• STS assertion only (no TA assertion)
The compressed address is driven on the external bus in the following manner:
• ADDR[0:29] = the word base address;
• DATA[0] = operating mode:
— 0 = decompression off mode;
— 1 = decompression on mode;
• DATA[1:4] = bit pointer
See Chapter 4, "Burst Buffer Controller 2 Module" and Appendix G, "MPC534
Compression Features" for more details about decompression mode.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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