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Bus Operations
CLKOUT
BR
BG
Receive bus grant and bus busy negated
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is sampled by slave
Figure 9-8. Single Beat Basic Write Cycle Timing – Zero Wait States
MOTOROLA
Chapter 9. External Bus Interface
9-13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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