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Queued Serial Peripheral Interface
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and
assumes its inactive state. At reset, the SCK baud rate is initialized to one eighth of the
IMB3 clock frequency.
Table 15-21 provides some example SCK baud rates with a 40-MHz IMB3 clock.
Table 15-21. Example SCK Frequencies with a 40-MHz IMB3 Clock
15.6.5.3 Delay Before Transfer
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or
user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of the
serial clock. The DSCKL field in SPCR1 determines the length of the user-defined delay
before the assertion of SCK. The following expression determines the actual delay before
SCK when DSCKL is in the range of 1–127:
A zero value for DSCKL causes a delay of 128 IMB3 clocks,
which equals 3.2 µs for a 40-MHz IMB3 clock. Because of
design limits, a DSCKL value of one defaults to the same
timing as a value of two.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transition is
one-half the SCK period.
15.6.5.4 Delay After Transfer
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also
be inserted between consecutive transfers to allow serial A/D converters to complete
15-38
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Division Ratio
SPBR Value
4
2
6
3
8
4
14
7
28
14
58
29
280
140
510
255
PCS to SCK Delay
NOTE
MPC533 Reference Manual
SCK
Frequency
10.00 MHz
6.67 MHz
5.00 MHz
2.86 MHz
1.43 MHz
689 kHz
143 kHz
78.43 kHz
DSCKL
=
------------------- -
f SYS
MOTOROLA
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