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Issues Regarding Power Sequence
V
DDH
V
DDL
V
cannot lead V
DDH
Figure K-8. Option B Power-Down Sequence with Keep-Alive Supply
K.9
Issues Regarding Power Sequence
K.9.1
Application of PORESET or HRESET
When V
is rising and V
DDH
tristated. Before V
DDH
V
is at least 3.1V greater than V
DDH
V
reaches 1.1V, and the 2.6 V drivers can start driving when V
DDL
these reasons, the PORESET or HRESET signal must be asserted during power-up before
V
is above 0.5 V.
DDL
If the PORESET or HRESET signal is not asserted before this condition, there is a
possibility of disturbing the programmed state of the flash. In addition, the state of the pads
are indeterminant until PORESET or HRESET propagates through the device to initialize
all circuitry.
K.9.2
Keep-Alive RAM
PORESET or HRESET must be asserted during power-down prior to any supply dropping
out of specified operating conditions.
An additional constraint is placed on PORESET assertion since it is an asynchronous input.
To assure that the assertion of PORESET does not potentially cause stores to keep-alive
RAM to be corrupted (store single or store multiple) or non-coherent (store multiple), either
of the following solutions is recommended:
• Assert HRESET at least 0.5 µs prior to when PORESET is asserted.
K-18
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
0.5-V lag
by more than 0.5V
DDL
is at 0.0 V, as V
DDL
reaches 1.6V, all 5 V outputs are unknown. If V
, then the 5 V drivers can come out of tristate when
DDL
MPC533 Reference Manual
Ramp down rates may
differ with load.
reaches 1.6 V, all 5 V drivers are
DDH
DDL
V
DDKAP
is rising and
DDL
reaches 0.5 V. For
MOTOROLA
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