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Table 10-1. Timing Requirements for Reduced Setup Time
CPU Specification
Short setup time = 2 ns
Normal setup time = 6 ns
Additional delay arising from on-board wires and clock skew between
internal clock and CLKOUT
10.2.6.1 Case 1: Normal Setup Time
Initial access:
Initial access time of memory
To derive the number of clocks required, divide by the system clock cycle time:
57
therefore 4 cycles are required
--------- -
=
3.18
17.9
Burst access:
Burst access time of memory
The number of clocks required
This case is illustrated in Figure 10-5.
10.2.6.2 Case 2: Short Setup Time
Initial access:
Enabling short setup time requires one clock cycle:
Initial access time of memory
The number of clocks required
required.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
+
Data setup time of CPU
+
Data setup time of CPU
20
therefore 2 clocks are required.
=
--------- -
=
1.11
17.9
+
Data setup time of CPU
53
=
---------- -
=
2.96
+
1(SST Enable Clock)
17.9
Chapter 10. Memory Controller
Memory Controller Architecture
Memory Device Requirements
Burst access time = 13 ns
+
Delays
=
50
+
6
+
1
=
+
Delays
=
13
+
6
+
1
+
Delays
=
50
+
2
+
1
=
53ns
therefore 4 clocks are
=
3.96
57ns
=
20ns
10-7
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