Data Storage Exception (0X0300) - Motorola MPC533 Reference Manual

Table 3-27. Register Settings Following a Machine Check Exception
Register Name
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Data/Storage Interrupt Status
Register (DSISR)
Data Address Register (DAR)
1
If the exception occurs due to an instruction fetch in Decompression On mode, the SRR0 register will contain the ad-
dress of the Load/Store instruction in compressed format. If the exception occurs due to an instruction fetch in Decom-
pression On mode, the SRR0 register will contain an indeterminate value.
2
DSISR and DAR registers are only updated when the machine check exception is caused by a data access violation.
When a machine check exception is taken, instruction execution resumes at offset 0x0200
from the base address indicated by MSR[IP].

3.15.4.3 Data Storage Exception (0x0300)

A data storage exception is never generated by the hardware. The software may branch to
this location as a result of implementation-specific data storage protection error exception.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Bits
1
All
1
2:4
10:15
Other
IP
ME
LE
DCMPEN
Other
0:14
2
15:16
17
18:21
22:31
2
All
Chapter 3. Central Processing Unit
Operating Environment Architecture (OEA)
Description
Set to the effective address of the instruction that caused the
interrupt
Set to 1 for instruction fetch-related errors and 0 for
load/store-related errors
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current implementation,
bit 30 of the SRR1 is never cleared, except by loading a zero
value from MSR[RI]
No change
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] and
BBCMCR[EXC_COMP])
Cleared to 0
Cleared to 0
Set to bits [29:30] of the instruction if X-form and to 0b00 if
D-form
Set to bit 25 of the instruction if X-form and to Bit 5 if D-form
Set to bits [21:24] of the instruction if X-form and to bits [1:4] if
D-form
Set to bits [6:15] of the instruction
Set to the effective address of the data access that caused the
interrupt
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