Rcpu Programming Model - Motorola MPC533 Reference Manual

RCPU Programming Model

3.6 RCPU Programming Model
The MPC500 architecture defines register-to-register operations for most computational
instructions. Source operands for these instructions are accessed from the registers or are
embedded in the instruction opcode. The three-register instruction format allows
specification of a target register distinct from the two source operands. Load and store
instructions transfer data between memory and on-chip registers.
MPC500 processors have two levels of privilege: supervisor mode (typically used by the
operating environment) and user mode (used by the application software). The
programming model incorporates 32 GPRs, special-purpose registers (SPRs), and several
miscellaneous registers.
Supervisor-level access is provided through the processor's exception mechanism. That is,
when an exception is taken (whether automatically, because of an error or problem that
needs to be serviced, or deliberately, as in the case of a trap instruction), the processor
begins operating in supervisor mode. The access level is indicated by the privilege-level
(PR) bit in the machine state register (MSR).
Figure 3-3 illustrates the user-level and supervisor-level RCPU programming models and
the three levels of the MPC500 architecture. The numbers to the left of the SPRs indicate
the decimal number that the instruction-operand syntax uses to access the register.
Note that registers such as the general-purpose registers (GPRs) are accessed through
operands that are part of the instructions. Registers can be accessed explicitly through
specific instructions such as move to special-purpose register (mtspr) or move from
special-purpose register (mftspr), or implicitly as part of an instruction's execution. Some
registers are accessed both explicitly and implicitly.
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