External Master
1. Request Bus (BR)
2. Receive Bus Grant (BG) from Arbiter
3. Assert Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drive Address and Attributes
6. Drive BURST Asserted
7. MTS Asserted (from MPC5xx Device
Drive data
ADDR[28:29] mod 4 =?
Assert BDIP
Drive Data
= 1
Assert BDIP
Drive Data
= 2
Assert BDIP
Drive Data
= 3
Negate Burst Data in Progress (BDIP)
Stop Driving Data
Figure 9-17. Basic Flow Diagram of a Burst-Write Cycle
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
= 0
Chapter 9. External Bus Interface
Slave
Receive Address
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Yes
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Yes
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Yes
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Yes
Bus Operations
No
Don't Sample
Next Data
No
Don't Sample
Next Data
No
Don't Sample
Next Data
No
Don't Sample
Next Data
9-25