Table of Contents
Advertisement
3.7.7
Count Register (CTR)
The count register (CTR), SPR 9, is used to hold a loop count that can be decremented
during execution of branch instructions with an appropriately coded BO field. If the value
in CTR is 0 before being decremented, it is –1 afterward. The count register provides the
branch target address for the branch conditional to count register (bcctrx) instruction.
MSB
1
2
3
4
0
Field
Reset
Addr
3.8
VEA Register Set — Time Base (TB)
The virtual environment architecture (VEA) defines registers in addition to the UISA
register set. The VEA register set can be accessed by all software with either user- or
supervisor-level privileges.
The VEA includes the time base register (TB), a 64-bit structure that contains a 64-bit
unsigned integer that is incremented periodically. The frequency at which the counter is
updated is implementation-dependent. For details on the time base clock in the MPC533,
refer to Section 6.1.7, "Time Base (TB)," Section 8.5, "Internal Clock Signals," and
Section 8.11.1, "System Clock Control Register (SCCR)."
The TB consists of two 32-bit registers: time base lower (TBL), SPR 268, and time base
upper (TBU), SPR 269. In the context of the VEA, user-level applications are permitted
read-only access to the TB. The OEA defines supervisor-level access for writing values to
the TB. Different SPR encodings are provided for reading and writing the time base.
MSB
0
Field
Reset
Addr
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
Figure 3-10. Count Register (CTR)
TBU
Figure 3-11. Time Base (Read Only)
Chapter 3. Central Processing Unit
VEA Register Set — Time Base (TB)
Loop Count
Unchanged
SPR 9
31 32
Unaffected
SPR 269, SPR 268
LSB
63
TBL
3-21
31
Advertisement
Table of Contents
